@***********************************************************************@
@				SRLOS Team All Right Reserved							@
@breaf:	this file as the assember language part of srlos boot program	@
@autor: bloceanc														@
@date:	07/06/2010														@
@com:	bloceanc@gmail.com												@
@***********************************************************************@
.section .text
.global	_start
.extern init_main	
.arm
_start:
@------------------------------------------------------------------------
@COMMENT:					##WARNNING##
@	Here we can't use L externed instruction, because we can't modify the value of
@value of LR(_mod)(R14_mod),it save the return address!
@	use B instruction, but is need an offset to PC for absourluton address.
@	the absourlution address at head of kernel!
@	more information see srl_head/head.s
@------------------------------------------------------------------------
	b _reset	@ reset handler, this must be at real address
	ldr pc, =0x105004	@ at virtual address, here is the handle of undef exception, assember code handle
	ldr pc, =0x105008	@ at virtual address, here is the handle of swi exception, assember code handle 
	ldr pc, =0x10500c	@ at virtual address, here is the handle of prefetch exception, assember code handle
	ldr pc, =0x105010	@ at virtual address, here is the handle of abort exception, assember code handle
	ldr pc, =0x105014	@ at virtual address, here is the handle of reserved 
	ldr pc, =0x105018	@ at virtual address, here is the handle of irq exception, assember code handle
	ldr pc, =0x10501c	@ at virtual address, here is the handle of fiq exception, assember code handle
_reset:
	@disable watch dog
	ldr r0, =0x53000000	@ watch dog address
	mov r1, #0x0		@
	str r1, [r0]		@ disable watch dog
	
	@disable interrupt
	eor r0, r0, r0		@ clear r0
	mov r0, #0xc		@ 0b11000000
	eor r1, r1, r1		@ clear r1
	mrs	r1, cpsr		@ r1 = cpsr
	orr r1, r1, R0		@ r1 = r1 | r0
	msr	cpsr_c, r1		@ cpsr = r1
	
	@initialize stack, as we'll use C
	ldr	r13, =4096		@ must < 4K.
	bl  init_main		@ call init_main
	
	@Enable MMU
	mrc p15, 0, r0, c1, c0, 0
	orr r0, r0, #0x1
	mcr p15, 0, r0, c1, c0, 0
	nop
	nop
	nop
	nop
	@here , it should running in SDRAM if success!..so this file also should load into SDRAM and mapping the same virutal address
	ldr r13, =0x104000	@reset sp, 0x1000 has been used as interrupt state stack, so use this tempary!
	ldr pc, =0x105000	@ the address(0x00105000) is vitual address!!!!!!!!cause we have enable MMU!!!
.end

	
